This invention relates to synchronization of clock timing signals in digital data communication systems operating with data signals defined by multidimensional signal sets, and more particularly to improved method and apparatus of generating timing phase error signals in demodulators of synchronous phase shift keyed (PSK) data receivers for adjusting the phase of a local clock timing signal there.
The receiver of a synchronous PSK data system generally equalizes the received signal prior to sampling during each symbol interval for recovering transmitted data. It is essential that timing in the receiver and the received signal be synchronized in order to insure optimum sampling of the received signal in each symbol interval, i.e., at a time when the phase of the signal is fully established and not in a state of transition. A number of conventional techniques are available for generating a local clock timing signal of the correct frequency in the receiver. By way of example, the amplitude of the received data signal may be detected and filtered to produce a local clock timing signal which has the same frequency as the timing signal used to generate the data signal. It is more difficult to make the phase of the local clock timing signal to the same as that of timing in the received data signal because of temperature and aging variations in timing circuits and the data path.
Timing phase error signals for adjusting the phase of the local clock timing signal have previously been generated and used in feedback loops. In the article "Timing Recovery in Digital Synchronous Data Receivers" by K. H. Mueller and M. Muller, IEEE Transactions on Communications, May 1976, pp. 516-531, samples of received data signals are processed to produce an indication of a timing function that is a measure of the pulse response of the data transmission system. This indication is used as the timing error signal for adjusting the clock phase in a direction for making the value of the timing function zero. The article states that the technique there is applicable to binary pulse-amplitude modulation (PAM) and partial-response signals, both of which are defined by unidimensional signal sets. In that method, only a single signal is available for processing to produce a timing phase error signal. The article does not teach how to extend the technique there for data signals that are defined by multidimensional signal sets. It also states that the discussion there is limited to baseband signaling, and concentrates on timing recovery alone and independent of carrier phase control, a synchronous carrier signal being assumed from external circuitry. The U.S. Pat. No. 3,544,717, Dec. 1, 1970, Timing Recovery Circuit by Larrabee M. Smith describes a timing phase correction technique in which the phase of a locally generated square wave timing signal is compared with transition pulses derived from received baseband mark and space type data pulses for driving a number of binary counters to produce control signals for advancing or retarding the phase of the local clock timing signal. The U.S. Pat. No. 3,633,108, Jan. 4, 1972, Timing Recovery Through Distortion Monitoring in Data Transmission Systems by Joseph G. Kneuer, describes a clock pulse correction technique with compensates for mistiming in the receiver eye pattern by generating caliper levels straddling a nominal received amplitude. The caliper spacing is continually expanded or contracted, depending on whether the received signals at sample times lie outside of or between the caliper levels. The phase of the sampling wave is made to sweep back and forth about its nominal position, the direction of the sweep being reversed whenever the caliper spacing requires expanding.